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| agilent technologies E2929B pci-x exerciser and analyzer technical overview key specifications o to 133.4 mhz clock speed 64 bit data and addressing exerciser (option #300) with full capabilities, including split transactions and 1mb data memory and real-time data generator unidirectional data path verification real time data compare fully pci-x compliant 53 pci-x protocol rules usb, rs-232, external 4mb fast host interface controllable in-system through pci-x plug-on pci-x state logic analyzer (option #100) with 2m state trace memory pci-x performance optimizer (option #200) realtime and post processed performance analysis system validation pack (option #310) with compliance tests c-api futureplus fs2104 for connection to agilent logic analyzers protocol permutator and randomizer software (option #320)
agilent E2929B pci-x exerciser and analyzer the E2929B pci-x exerciser and analyzer provides r&d and qa engineers with a fast and predictable way to debug, optimize and validate pci-x based designs, like servers, motherboards, chip- sets, raid systems or network interface cards. the modular test card combines a pci-x protocol checker, a pci-x exerciser (option #300) with full requester and computer capabilities to generate any kind of pci-x transfer and a pci-x state logic analyzer (option #100). in addition, a logic analyzer adapter (futureplus fs2104) is available, adding pci-x protocol check and analysis capabilities to your agilent 16700 la. individual software modules address specific needs during design bring up, design validation and compliance testing. verification of pci-x protocol compliance the E2929B features a pci-x protocol checker, which runs constantly, checking for pci-x protocol rule violations in real-time. in total, 53 protocol rules are checked concurrently. all rules are derived from the pci-x and pci specification. thus, just plugging the E2929B into a pci-x system and activating the pro- tocol rule checker allows you to check for pci-x protocol compliance. the E2929B reports a list of all the errors that have occurred. for the purpose of debugging, the protocol checker can be used to trigger either the plug on state logic analyzer (option #100) or an external logic analyzer. also, each individual protocol rule can be masked. predictable system and chip validation the E2929B pci-x exerciser (option #300) features a fully controllable requester and computer, real-time data compare and the agilent patent- ed protocol permutation and randomizing technique. this allows engineers to validate and stress the pci-x system with specific and fully repeatable test cases. efficient design debugging to get an insight into your system, a simple click of the mouse is all that is needed to setup a specific trigger or the pci-x plug-on state analyzer (option #100). alternatively, you can connect the E2929B to your agilent 16700 logic analyzer system using the futureplus fs2104 logic analyzer link. the plug-on pci-x state analyzer offers impressive trigger and storage qualifier capabilities. this makes it easier to find complex error conditions. besides conventional pattern terms for all pci-x signals, an additional bus observer makes the current bus status (e.g. address phase, attribute phase, data phase, idle phase etc.) transparent, and thus simplifies the setup of trigger conditions. combining additional error pattern terms, external trigger inputs and trigger sequencer capabilities, the E2929B gives you the ultimate power to capture the data you need. system benefits easy pci-x system evaluation windows based gui for interactive use plug-on pci-x optimized state analyzer optimize design and test corner cases pci-x exerciser stresses your system's corner cases predictably and repeatedly easy system validation using ready to run tests over 1,000,000 test cases in less than 5 seconds 1 programmable in-system c-application programming interface system overview the e2929a is a short pci-x card, which can simply be plugged into the system under test. it is controlled by an interactive graphical user interface or from a specific customer c program (option #320 required). the software can either be installed on the system under test itself - controlling the E2929B through the pci-x system bus, or on an external host - controlling the E2929B either by usb, rs-232 or a 4mb/s fast host interface, designed for a high data transfer speed. test case @133mhz = (50 clocks delay + avg. 250 clocks for 2k bursts) *7.5ns = 2.5us. thus, 1,000,000 test cases need = 2.5s + 2s setup time. pci-x protocol checker the E2929B basic configuration supports the pci-x protocol checker which checks 53 pci-x protocol rules in real-time. each rule can be individually masked to suppress the triggering of known problems. the rules are derived from the pci-x specification 2 , and are designed to find any possible violations of the pci-x protocol. when a protocol violation is detected, the protocol checker can: store the rule number of the first (non-masked) violated rule list all found protocol errors accumulate the number of violated rules directly trigger the plug-on pci-x state analyzers trace memory (option #100) directly trigger the futureplus fs2104 pci-x addendum to the pci local bus specification revision 1.0, september/22/1999 figure 1: E2929B figure 2: protocol checker !"# $% & '' ' & ( ) % " * ) (( + ) ) ( , !"#$% ' '- & ) . , /) 0 ) !"#$% ' '- & ) 1 , ) 0 ) 02 !"#$% ' ' - & ) 3 2) 4 % " ) % ( !"#$% & 1 ' , ( ( %( ! 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' ) 3 & ) 1 5 6 ) . . ) 6 < '1 ) 5 pattern terms can be combined with logical operations and, or and negation. the termination counter can be pre-loaded and decrement. flexible trigger points for maximum flexibility, the trigger can be placed in any position in the trace memory external trigger i/o 4 trigger i/o signals provide a way to synchronize between multiple pci / pci-x test cards of the e2920 series, req# and gnt# lines of other pci / pci-x devices or other test equipment like a general-purpose logic analyzer. programmed as input pins, they are observed by the state analyzer and are available as part of the pattern terms. figure 4: trigger gui gui or c-api control the plug-on pci-x state analyzer comes with a windows based gui (graphical user interface) and cli (command line interface). it can be controlled through the optional c-api (option #320). the command line interface (cli) allows you to interactively control the pci exerciser and analyzer by entering command func- tions that correspond with the func- tions provided by the c-api. the cli can also process batch files of concatenated command functions. futureplus pci-x analysis probe with the futureplus pci-x analysis probe, the E2929B pci-x protocol checker becomes an integrated part of your 16700 logic analyzer system. with the analysis probe, which is simply plugged onto the E2929B, each pci-x signal is passed to the 16700 logic analyzer system, together with a protocol error signal. this is the opti- mum solution whenever cross-correla- tion between the pci-x bus and other system interfaces is needed for effi- cient system debugging or software development. the analysis probe and E2929B are controlled by the logic analyzer. the probe features: connectors to the 16700 logic analyzer dip switches to mask individual pci-x protocol errors led bank to indicate individual protocol errors protocol checker reset futureplus analysis software running on the agilent 16700 logic analyzer systems. whenever the probe is connected to the E2929B, the E2929B automatically switches into continued pci-x protocol error check and bus sampling mode. thus, set-up is as easy as plugging the E2929B into the pci-x slot and connecting the logic analyzer. pci-x performance optimizer (option #200) this optional package extends the agilent E2929B with performance measurement capabilities. using the pci-x performance optimizer in-depth post processed statistical performance analysis can be done. for this analysis, one or multiple bus snapshots are taken by the pci-x analyzer. optimize system performance statistical pci-x performance analysis makes it easy to select the best pci-x cards and components, detect and locate pci-x performance bottlenecks, and balance system settings so that the overall performance of the system is optimized. a hierarchical approach to analyzing post-processing performance measurements is used. this means that the agilent E2929B can move swiftly from high-level throughput numbers to, for example, pci-x command usage and latency measurements, as required. it is therefore simple to identify design issues and analyze their causes. overall, this approach reduces the effort required in revealing design problems. ? graphical and text-based presentation ? in-depth performance analysis through post-processing ? first word latency measurement ? reveals completer and requester contribution to performance measurement results ? split statistics ? measures overall traffic and selective for requester/completer pair ? report generation ? cross-references to pci-x analyzer graphical user interface post-processed data analysis the E2929B can carry out an in-depth performance analysis of sampled pci-x transactions by using the pci-x analyzer to acquire data. basic bus statistics to obtain an overall picture of the pci-x performance, the pci-x bus is analyzed for: ? pci-x throughput ? pci-x utilization ? average first word latency ? pci-x efficiency ? average split rate ? pci-x data efficiency 3 the analysis probe is not an agilent product. agilent works closely with futureplus to ensure quality products. but the vendor is responsible for functionality, pre-sales and post-sales support and warranty figure 5: performance windows: setup, report and charts a bus efficiency chart provides an overview of how efficiently the traffic was handled between different bus agents. bus utilization the bus utilization analysis shows how the pci-x bus was used by: ? data transfer ? overhead a utilization chart shows how the different bus agents used the bus. requester/completer performance post-processing allows the analysis of customer-selected requester/ completer combinations so that specific requester/completer performance behavior can be analyzed in depth. by evaluating the critical agents using the real-time measurements and basic bus statistics, the in-depth requester/completer analysis provides an inside view of how to optimize single agents. latency histogram a latency histogram shows the fraction of transfers that had a certain sequence length and first word latency. split transaction statistics number of split sequences and average values of first word latency, length and time overhead as well as a statistic of pending requests over time. overhead statistics states if requester or completer was the cause of a certain fraction of overhead. burst length distribution this histogram also shows the distribution of burst length over pci-x commands. again, this provides an inside view into performance bottlenecks in pci-x systems. this is observed per sequence as well as per transaction. command usage chart the command usage chart lists the usage of different pci-x commands so that performance issues caused by inefficient command usage are revealed. requester/completer efficiency a further important indication for pci-x system performance is how efficiently a certain requester/com- pleter pair uses the occupied bus time. thus, the software examines: ? requester/completer overall efficiency of transferred data ? efficiency over burst length. termination statistics the pci-x termination statistics indicate: ? termination over command. ? cause of termination (imitator/ target) over burst length. report and result ascii-file all results are available as an ascii report file for further analysis and customer post-processing. the different segments are: 1 general information 1.1 test base 1.2 statistical base 2 basic bus statistics 3 bus throughput statistics 4 efficiency statistics 4.1 requester completer efficiency 4.2 64 bit bus statistics 5 bus utilization statistics 5.1 requester completer utilization 6 bus users overview7 split transaction statistics 7.1 pending requests over time 8 requester - completer pair: pci-x exerciser (option #300) the agilent E2929B has an optional on-board 64 bit pci-x exerciser. the exerciser operates at 0 to 133.4 mhz, and can emulate and force practically any behavior of a pci-x device imaginable- except blatant protocol violations. the exerciser comes with a graphical user interface (gui) and a command line interface (cli). as an option, the exerciser can be con- trolled from a c-api (option #320). the exerciser features: two requester queues one computer four completer queues to handle independent split-transactions one requester-target handling up to 32 open requests requester and computer are fully programmable, operate independently of each other and are able to handle: 32/64 bit data transfers 32/64 bit addressing programmable delays between transactions block length up to 4gbyte all 16 pci-x command types requester initiator data block the requester initiator data block settings define which address space is accessed, and where data is moved. up to 256 block transfers can be defined and performed in a linear sequence by one of the two transfer queues. each block specifies: the bus command seen on c/be[3::0] in the address phase. all valid pci-x commands are supported the 64 bit bus address the byte enable value (c/be[3::0] / c/be[4::7] the start address of the data memory or if the data generator is used the number of bytes to be transferred (1 to 4gb) if the real-time data compare for incoming data should be activated the start condition for the transfer (immediately or wait for event) the transfer queue the data is passed through requester initiator behavior the requester initiator behaviors are set to specify the pci-x transfer behavior per address/data phase. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: 32 or 64 bit data access insertion of 1 to 65535 clock cycles delay between transactions the next data queue to be used if an automatic or customer defined tag (0..31) is used architectural overview the exerciser is based on two main ideas. firstly, defining requester initiator data blocks, describing 'what' data should be transferred and secondly, defining a requester initiator behavior, describing how the transfer should be executed. for the requester initiator, up to 256 blocks of data transfers can be set up (see figure 2). in addition, requester initiator behaviors are set up, specifying how the requester initiator intends to transfer the data blocks over the pci-x bus. if any completer target replies to a transfer and requests a split transaction, the requester initiator data block attributes are moved internally to a split transaction map for further use. the transaction map can manage up to 32 open split transactions. when completing split transactions, the requester target behaviors are used to control the transfer. the completer target behavior attributes define how the completer target of the E2929B acts. the completer target can manage up to 4 split transaction queues. it is also possible to fully control initiating the completion of split transactions. the completer initiator behavior attributes are used to program it. the programmable transaction scheduler decides whether completer or requester transaction is performed. all data comes or goes through the on-board data memory or from the on-board real-time data generator configuration space the E2929B provides configura- tion space, which is fully pro- grammable. default values (cus- tomizable) are stored in an eep- rom on-board and are used to initialize the configuration space when the power is on. the configuration space can be disabled, making the card invisible to bios or o/s configuration routines. thus, analysis tests are possible without having any effect on the device or system under test. the specific burst length for the transfer ( 1 to 4096 byte) automati- cally rounded up to the next qword boundary the n-th adb where the requester initiator disconnects (1 to 32) perform 0 to 4 address steps how many clock cycles after the address phase req# is de-asserted (0 to 2047) how often the current transfer attributes are used (repeat value 1 to 256) latencies between requester initiator transactions the latencies between transactions can be varied using requester initia- tor behavior property. the minimum latency is in general 1 clock cycle - including any sequences of read/write where real-time data compare is involved. the only exception is if the most recent transaction is a read/write transfer into data memory and the subsequent transaction is a write out of data memory. in this par- ticular case, the latency is 10 to 20 clock cycles. please note that it is assumed that the master does not need to discon- nect before the byte count of the cur- rent sequence is transferred and that wait cycles are added if required by the pci-x specification. requester target behavior the requester behavior attributes are set to specify the pci-x transfer behavior per address/data phase if a target requests the completion of a split transaction from a requester initiator. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: the decode speed used (a 4 /b/c) acknowledgement of 64 bit data transfers the number of initial latency clock cycles (3 to 34) the behavior after initial latencies, either accept transfer, disconnect, signal retry or abort how often the current behavior is applied (repeat value 1 to 65536 s p lit tr a n s f e r ma p re q ueste r initiat or data bloc k s p lit transactio n t ar g e t mana g emen t re q uester initiat or behavi or c om p leter initiat or behavi or transa c ti o n sc he d ule r data memor y dat a com p ar e d ata g enerat or com p lete r tar g et behavi or re q ueste r tar g e t behavi or de cod e r p c i-x b us q ueue 4 q ueue 3 q ueue 2 q ueue 1 q ueue 2 q ueue 1 completer target behavior attributes the completer target behavior attrib- utes give full control over the E2929B completer target behavior, and define how it reacts to a request. up to 256 attribute entries, which can be setup as linear sequences or repeat loops, are allowed. the attributes control: the decode speed used (a 4 /b/c) acknowledgement of 64 bit data transfers the number of initial latency clock cycles (0 to 31) the behavior after initial latencies, either accept transfer, signal a single data phase, retry or abort the behavior in subsequent data phases, either accept all subsequent data phases, disconnect after 1 to 2047 data phases signaling a split response, either by identifying an address value or range in the address phase, the decoder accessed, or by a subset of all 16 possible pci-x commands the split transaction queue to be used how often the current behavior is applied (repeat value 1 to 65536) configuration space and decoders in total, the E2929B features 5 decoders: one standard configuration space decoder, fully customer programmable 3 programmable target decoders (six bars) that can either hold up to 3 memory spaces (64 bit) or 2 memory spaces and 2 i/o spaces simultaneously one decoder to access the 64kbyte expansion rom completer initiator behavior the completer initiator behavior attributes are set to specify the pci-x transfer behavior per address/data phase if a completer target starts to complete a split transaction. up to 256 behavior entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: the split transaction queue to be served the start condition for this transfer 32 or 64 bit data transfer ! "#$%%&%' ! "#()*' "$' # %$' +,"#&' decode speed a is supported up to 66 mhz figure 6: E2929B option #300 pci-x exerciser architecture completer target latencies the initial latencies can be programmed with the completer target behavior attributes. depending on the selected decode speed and address phases, the test card automatically adds the needed number of wait states to achieve the defined initial latency. a minimum of one wait cycle is always added when using decode speed b or c and a minimum of two wait cycles are needed with decode speed a. in case the subsequent target access is a 'read from target' and the most recent event was a 'write to target', 'read from other target address', 'master write' or 'master read', the minimum initial latency is 15 clock cycles. data memory the E2929B option #300 features a 1mb (128k x 2 dwords) programma- ble read/write data memory. master / requester and target/ completer share the memory. the address decoders can selectively address it. the data memory can: store data from read/write transfers be mapped to any pci-x address space data generator instead of using the data memory, the on-board data generator can be used. without initial latencies, the generator can generate a data pattern, deterministically linked to the data address. combined with a second exerciser card and the real- time data compare feature, long-time load stressing on any pci-x to pci-x data path can be performed while errors are detected in real-time (figure 3). the generator features the following patterns: walking ones or zeros ground bounce count up (unique data) pseudo random pattern (unique data) the count up and pseudo random pattern are unique up to the length of 1m quad words (4mb). the data uniqueness is derived out of the lower real-time data compare real-time data compare can be per- formed either on: memory: when data is written to the memory it is compared against the actual memory content data generator: based on the data address the generator calculates the expected data and compares it with incoming data. exerciser graphical user interface the graphical user interface gives you an easy way to setup and control the exerciser. master conditional start 5 the master conditional start window allows you to set up the start conditions for the master traffic. following a run command, the master can be programmed to start: immediately triggered by a pattern target decode window the target decode window lets you configure the target address decoders. as well as configuring the programmable decoders for the exerciser's on-board memory, you can individually enable or disable the decoders for configuration space and expansion rom. you can also store the current settings as defaults, which will then be used following all subsequent power cycles or pci-x resets. error injection capabilities the E2929B is capable of injecting error conditions into a system includ- ing generating inverted parity (par and par64), signalling a parity error (perr#) or a system error (serr#) in a specified phase of the transac- tion. figure 7: exerciser gui 5 supported by gui with software revision 2.0 figure 8: undirectional data path verification figure 9: exerciser generic settings - ./012 3 4 5 ./01 - 2 6 - - 2 7#$ & $) 3 - agilent system validation package (option #310) the system validation package is a ready-to-use software package, which performs system stress tests during the validation of servers, worksta- tions, pcs, or other pci/pci-x based systems. with its easy-to-use windows-based gui, it simplifies test development on setup for engineers and allows easy test execution by technicians. choosing the agilent e2925b, e2928a, e2940a, E2929B option #310 adds the system validation package to your hardware order. target application the system validation programs and controls multiple pci/pci-x exerciser and analyzer test cards of the e2920 pci series to create realistic application system traffic. the test card approach allows you to set up fully predictable traffic scenarios and gives you measurable test coverage and test predictability. used for validation of pci/pci-x based sys- tems and silicon, it enhances the traditional test method of using off- the-shelf pci/pci-x cards. outstanding test coverage todays validation test methods typically lack time efficiency and repeatable execution of critical system traffic scenarios. hot mock-up tests, which use off-the-shelf pci cards to load a system-under-test and wait until an error occurs, are the typical test approaches used today. now the system validation executes such types of system critical tests within minutes, simply with a mouse click. ppr, the key technology agilents protocol permutation and randomizing (ppr) technology is the key to predictable and repeatable test coverage. ppr is technology that allows permutation of the pci/pci-x protocol and traffic in a determin- isitic way. thus, system critical test patterns are not only transferred between different system components, but also automatically permutated to achieve all possible traffic scenarios. stress all critical data paths just by plugging the pci/pci-x exerciser and analyzer test cards in each individual pci/pci-x bus of your system under test, the software is able to automatically test and stress data paths within your system (see figure 1). a small executable running on the system cpu(s) allows testing within the whole system, not only the i/o system, while tests are run from an external controlling host. system validation package/system test library benefits ? fully controlled test environment for validation of servers, worksta- tions and pcs ? predictable test coverage ? repeatable test scenarios ? documented test results figure 10. system architecture test method the agilent system validation allows automatic tests and stress data paths from: ? cpu and exerciser to system memory ? exerciser to system memory ? cpu to exerciser memory space ? cpu to exerciser i/o space ? peer to peer traffic ? master to target traffic ? load generation while testing, the setup emulates typical traffic scenarios in a pci system. for example, data cpu to scsi card, lan to lan card traffic, concurrent system memory access from lan card and cpu (see figure 2). so far, these have been typical traffic scenarios and have been generated within the so-called hot mock-up test. now the agilent verification solution significantly extends this validation process by: ? increasing test coverage through increased number of variations, when dealing with system traffic. ? being programmable to force the systems most critical traffic conditions. ? being repeatable for failure analy- sis and failure regression tasks. ? being comparable, to achieve mea- surable quality improvements. ? producing log files to catch the problems before the system hangs. ? creating test reports to document system quality. ? making an easy link to r&ds debug environment. any access from an agilent exerciser is permutated using ppr, varying block sizes, memory commands, alignments, and byte-enables (mean- ing all variations of dword, word, and byte read/write accesses are used). protocol variations on all system actions include waits/latency, termina- tions, 64 bit and 32 bit access, address/data stepping and as w ell as acceptance/non-acceptance of 64 bit access . automatic test setup when starting the validation software on a system under test, it automatically scans the system for agilent pci/ pci-x exerciser and analyzer cards. based on the available test cards, the operator can select various tests, define the test duration and start the test. customer configurable tests all tests are configurable by the customer. the gui shows all parame- ters, and all setups are simply done with a mouse click. thus, using different exercisers to test between different buses, e.g. 33 mhz pci and 133 mhz pci-x, is easy. with each test, you just select the path to test. the software auto- matically comm unicates with the test card plugged into the corresponding bus and tells you which protocol/traf- fic parameters you may vary. figure 11. test card setup 14 tests available pcisig compliance tests the agilent system validation package includes a series of tests defined by the pci special interest group (pci-sig). agilent technologies has been work- ing closely together with the pci-sig to provide compliance tests, which are utilized, for testing pci and pci- x systems at each pci-sig compliance workshop. agilent sup- plies the hardware and software to perform pci-sig compliance testing, including a pci-sig compliance test library. the tests are used to verify that devices and systems are compli- ant to the pci and pci-x specifica- tions. the tests are set up and run via the system validation package combined with either the pci or pci- x exerciser/analyzer test cards. these tests are in addition to the standard tests included or part of the system validation package option. description of the compliance tests: - mlt - master latency test this test is not implemented as a special test within svp but can be carried out manually. to do this, carry out the pci configuration scan test (see "pci configuration scan" on page 50) and examine the latency settings to determine the result of this test. sig post test this test is utilized to initialize the base address registers and to verify the address assignments. to do this, the test card is defined as target. sig interrupt routing test the exerciser asserts an interrupt on request from the analyzer mailbox. to do this, the test card is defined as a master. the svp software requests an inter- rupt from the card and verifies that the interrupt was received and processed correctly. cpu to test card address and test card to system memory address this test accesses either the memory space or the i/o space of the test card from the cpu. to do this, the test card is defined as a target. this test also accesses the system mem- ory from the pci or pci-x bus. to do this, the test card is defined as a master and sends different write and read commands from/to the analyzer. sig card test the sig card test performs a number of tests. this includes testing for: correct values and operation for the command register. the status register. appropriate values for other configu- ration registers. the configuration register contents are displayed during the sig card test in the svp reporting window that opens when you run the test. pmtest - power management test type1 - type 1 test the type 1 test verifies correct configu- ration transaction decoding by the device. discard - discard test this test verifies that the card correctly repeats retried pci transactions. discard - discard test this test verifies that the card correctly repeats retried pci transactions. for more information about the pci- sig compliance program and the agilent system validation package, please refer to www.agilent.com/find/pci_svp or to www.pcisig.com 12 further tests the following list describes all tests available for the system validation. all tests are customer configurable (see table 2, page 12), and stress one data path. all tests can be performed concurrently to increase and maxi- mize stress conditions. the ppr capa- bilities vary from exerciser model to exerciser model. for example, differ- ent protocol variations are available for pci and pci-x. please refer to the corresponding technical data sheet of the exerciser used for a list of available protocol variations. cpu and exerciser to system memory access system memory space via virtual memory from cpu and from pci/pci-x bus (exerciser acting as master). the same address range with interleaved addresses is used in order to stress cache controller. ? tested data paths: cpu to host mem- ory; exerciser to host bridge to system memory. ? tested devices: host bridge and host bridge configuration, host memory controller, and arbitration unit. w/r/c to system memory access the system memory from the pci/pci-x bus, and perform data write/data read/data compare. ? tested data paths: exerciser to host bridge to system memory ? tested devices: host bridge, host bridge configuration, host memory controller, and arbitration unit read from memory this test reads repetitively from a customer-defined physical address to check accessibility and to stress the data path: ? tested data paths: exerciser to host bridge to system memory ? tested devices: host bridge, host bridge configuration, host memory controller, and arbitration unit peer-to-peer traffic two pci exerciser cards access each others memory or i/o space. master- target traffic in both directions is set up. two test cards on different buses are used to test the bridges and bridge configuration. ? tested data path: exerciser #1 to bridge(s) to exerciser #2 ? tested devices: bridges, bridge con- figuration, and arbitration units master target traffic two pci exerciser cards access each others memory or i/o space with unidirectional master-target traffic. two test cards on different buses are used to test the bridges and bridge configuration. ? tested data path: exerciser #1 to bridge(s) to exerciser #2 ? tested devices: bridges, bridge configuration, arbitration units cpu to test card this test accesses either the test cards memory or i/o space via virtual memory from the cpu. ? tested data paths: cpu to host bridge to test card ? tested devices: host bridge, host bridge configuration, host memory controller, and arbitration unit bus load generation an exerciser is set up to generate self-traffic and therefore saturate a bus with a defined level of traffic. this kind of test stresses other devices on the same bus by limiting the avail- able time a certain device can get access to the bus. also the arbitration unit can be verified under controlled bus load conditions. error analysis the analyzer of an e2920 series test card can be set up to check for: ? protocol violations ? data transfer errors ? parity errors ? bus hang-ups/bus locks ? bus load measurements detected problems are logged in a report file. optionally, a trace memory waveform file is generated for in-depth root cause analysis. all pci/pci-x devices on the bus are passively observed. figure 12. test scenario setup window in-system programmable the agilent system validation can be installed and executed on the system- under-test itself. in this case, the exerciser and analyzer are pro- grammed through the pci and the pci-x interface. external control alternatively, the whole test can also be controlled from an external host pc, which runs the system validation. the exerciser and analyzer are connected via an appro- priate external interface (rs-232, 4mb fast host interface). to execute a test that requires the fsi (see table 2), the fsi must be installed on the system under test. working with non-windows os two options are available to verify a system that does not use windows. use an external controlling host pc in this case, any test which does not require the fsi can be executed immediately. to use the other test, the fsi, which is only a small c-program, must be compiled for the appropriate os. the fsi is delivered as executable for windows dos, and in source code. porting the system test library the other alternative is to import the complete system test library to your preferred os. therefore, the system test library comes with source code. optionally, special porting support is offered, helping you to incorporate the system test library test capabilities into your proprietary test environment. table 2. customer configurable test parameter customer configurable test parameters usable mechanisms to detect errors # of fsi 2 band- ppr address address address memory data protocol protocol capture cards width space prefetch size compare check error waveform mask on error 3 cpu and 1 yes 1..100% memory n/a by os 0..512kb/ test card to 0..1mb 1 system memory peer to peer 2 no 1..100% memory true or by bios/ 0..512kb/ test or i/o false os 0..1mb 1 master/target 2 no 1..100% memory true or by bios/ 0..512kb/ traffic or i/o false os 0..1mb 1 cpu to test 1 yes 1..100% memory true or by bios/ 0..512kb/ card or i/o false os 0..1mb 1 write/read/ 1 yes 1..100% memory n/a by os dword compare to value system memory 0..4kbyte read from 1 yes 1..100% memory n/a address dword system memory value value 0..4gbyte bus load 1 no 1..100% memory n/a by bios/ 0..512kb/ ? generation or i/o os 0..1mb 1 (self traffic) 1. the memory can be specified for the selected exerciser. 512kb data memory is available on e2925b, e2928a, and e2940a. 1mb da ta memory is available on E2929B 2. the fsi (front side interface) is a small executable table which must run on the system under test cpu(s). 3. requires option 100 for the E2929B. not available for e2922a. required e2920 series exerciser/analyzer the system validation package requires a full exerciser/ analyzer (see table 3). ordering information the system validation package can be ordered as option #310 of the e2925b, e2940a, e2928a, and E2929B the system test is also available as a system test library to be integrated in customer proprietary test frames. refer to system test library techni- cal specifications (5968-3500e) for more information. table 3. minimal exerciser/analyzer configuration needed for option #310/system test library option #310 system test library E2929B pci-x protocol checker ?? #100 (analyzer) ?? #300 (exerciser) ?? #320 (c-api) ? e2925b/e2940a/e2928a pci ?? #300 (exerciser) ?? #320 (c-api) ? e2922b pci-x master target test cards ? 1, 2 1. for error detection, the e2922b supports pci-x protocol and data compare only. other analyzing capabilities like waveform capture, trigger i/o, or bus load measures require the E2929B. 2. the e2922b does not support external interfaces and must be in-system programmed through pci-x. -.. 2 /.0 ./01 5 0 - .. 0 5 - 8 2 9 - .. : 2 2 - 0 2 02 - - 3 , 2 5 /.; c-api / ppr (option #320) - / . 0 "/.0' 2 3 < !&( / 2 3 < !&( ./0. . 3 - 2 0 2 , ;=, =& 2 0 ./01 - , >?=@ /aa@$( effective test generation the exhaustive c-library makes it simple to focus on test structuring, partitioning and the specification of protocol constraints. this means that an appropriate and valuable test for protocol verification with meaningful results can quickly be obtained. once started, the test can easily be extended to incorporate newly gained experiences or to address testing needs for newly invented pci-x features. deterministic test conditions in contrast to pci-x traffic generated by other pci-x cards, the generated variations are completely deterministic and reproducible. supported protocol variations the exerciser and analyzer allow the variation constraints for the pci-x transfer, pci-x master/requester and pci-x target/completer behavior to be specified. all specified constraints can be permutated against each other and up to 100 constraints can be maintained per list. pci-x transfer variations the generator features the following algorithms: start address alignment; a list of arbitrary address alignments to start pci-x transfers at given offsets (e.g. 1 dword) relative to the q word boundaries byte enables; a list of selected values for the c/be lines during the address phase block size; a block describes a contiguous range in memory avail- able to be transferred. a list of up to 100 different block sizes (from 1 to 4096 byte) can be selected to be transferred bus commands; a list of selected pci-x bus commands. all selected commands are permutated with other selected constraints, as appropriate, for the specified transfer direction and pci-x specifications permutation of release ordering bit permutation of no snoop bit. target behavior variations the requester initiator allows for the variation of: byte count (1 to 4096) disconnect/initiator termination delay address stepping req64 release req the completer initiator allows for the variation of: error message, yes/no partitioning delay address stepping req64 release req general specifications pci-x specifications: pci-x bus: 32/64 bit addressing: 32/64 bit pci clock range: analyzer: 0 to 133.4 mhz exerciser: 0 to 133.4 mhz the E2929B fully meets timing specifications for 133 mhz pci-x. electrical specifications: for 3.3v environment, complies with pci-x spec. 1.0. decoupling: unused 3.3 v power pins are decoupled. power requirements: consumes less than 25 w from pci-x slot. trace length limits: meets pci-x specifications. signal loading: less than 10 pf, fully pci-x compliant. operating temperature: -40c to +55c. mechanical dimensions: short card, occupying one slot. system requirements: software supports microsoft windows 2000, 98 and xp. , 5 , - 3 ) ' & ) ' & - . f ) #6-g" h..g" ordering information E2929B base product includes: 32/64 bit, 0..133.4 mhz pci-x protocol checker rs-232, usb protocol checker graphical user interface for windows software media cd option #100, pci-x plug on state analyzer includes: plug-on pci-x state analyzer piggy pack board analyzer graphical user interface for windows 4mb/s fast parallel interface software media cd option #200, performance optimize 6 includes: single user license software media cd option #300, pci-x exerciser includes: customer installable single card license enables on-board 32/64 bit, 0..133 mhz exerciser hardware exerciser graphical user interface for windows software media cd when ordering without base product, s/n of the existing e2929a must be notified on purchase order. option #310, system validation 6 includes: single user license graphical user interface for windows . the pci-x exerciser (option #300) must be installed software media cd customer installable single card license enables ppr hardware and c-api interface for one test card the pci-x exerciser option #300 must be installed drivers for windows porting support is available to port c-api to linux, hp-ux or proprietary operating systems. contact your local sales offices for detailed information.when ordering without base product, s/n of the existing E2929B must be notified on purchase order. accessories external power supply e2991a the external power supply supports applications where the exerciser and analyzer card should be transparent to the system, you can connect this external power supply to prevent the card from drawing power from its slot. futureplus analysis probe 7 fs2104. available from agilent as resell part fsi 60042 6 with software revison. 2.0 * the analysis probe is not an agilent product. agilent works closely with futureplus to ensure quality products. but the vendor is responsible for functionality, pre-sales and post sales support and warranty pci analyzer -protocol checker - 64k state pci logic analyzer -4mb fast host interface - timing checker -real-time performance measures -gui - rs-232 interface e2940a compact pci 32/64 bit 66mhz e2925b pci 32 bit 33 mhz e2928a pci 32/64 bit 66 mhz E2929B pci-x 32/64 bit 133 mhz -protocol checker -rs-232/usb interface - gui opt.100 pci-x analyzer - 2m state pci logic analyzer -4mb fast host interface -real-time performance measures - gui opt..200 pci performance optimizer 4m trace memory recommended please order separately 32/64 bit 66 mhz pci-x performance optimizer -post processed and real-time performance analyzer -performance report - gui opt.300 pci exerciser - master and target -gui - cli -512 kb on-board memory 32/64 bit 33 mhz 32 bit 33 mhz 32/64 bit 66 mhz pci-x exerciser - master - target - gui - 1mb onboard data memory opt. 310 system validation package - peer-to-peer test -system memory test - system load test - protocol load test - protocol check - gui opt.320 c-api/ppr - c-programming interface library -protocol permutation and randomization library overview pci/pci-x e2920 series pci-pci-x bundle: with the e2997a agilent also offers a great price on the purchase of the e2928a pci card and the E2929B pci-x card. master target test card the e2922b pci-x master target test card provides validation engineers in the semiconductor industry a fast and predictable way to set up pci-x protocl compliance of first silicon. ! " agilent technologies' test and measurement support, services, and assistance agilent technologies aims to maximize the value you receive, while minimizing your risk and problems. we strive to ensure that you get the test and measurement capabilities you paid for and obtain the support you need. our extensive support resources and services can help you choose the right agilent products for your applications and apply them successfully. every instrument and system we sell has a global warranty. support is available for at least five years beyond the production life of the product. two concepts underlay agilent's overall support policy: "our promise" and "your advantage." our promise our promise means your agilent test and measurement equipment will meet its advertised performance and functionality. when you are choosing new equipment, we will help you with product information, including realistic performance specifications and practical recommendations from experienced test engineers. when you use agilent equipment, we can verify that it works properly, help with product operation, and provide basic measurement assistance for the use of specified capabilities, at no extra cost upon request. many self-help tools are available. your advantage your advantage means that agilent offers a wide range of additional expert test and measurement services, which you can purchase according to your unique technical and business needs. solve problems efficiently and gain a competitive edge by contracting with us for calibration, extra-cost upgrades, out-of-warranty repairs, and on-site education and training, as well as design, system integration, project management, and other professional services. experienced agilent engineers and technicians worldwide can help you maximize your productivity, optimize the return on investment of your agilent instruments and systems, and obtain dependable measurement accuracy for the life of those products. related agilent literature agilent e2925b 32bit, 33 mhz, pci exerciser & analyzer, technical specifications, p/n 5968-3501e agilent e2928a 32/64bit, 66 mhz, pci exerciser & analyzer, technical specifications, p/n 5968-3506e agilent e2940a compactpci exerciser & analyzer, technical specifications, p/n 5968-1915e agilent e2922b pci-x master target card, technical overview, p/n 5968-9577e agilent system validation pack, agilent system test library, technical overview, p/n 5968-3500e agilent e2920 computer verification tools, pci series, brochure, p/n 5968-9694e intel discusses basic concepts of pci performance and efficient use of pci with the agilent e2920 series, case study, p/n 5988-0448e hp nsd stabilizes server designs quickly and completely with the agilent e2920 pci series, case study, p/n 5968-6948e hp hstc speeds high-end server testing and reduces engineering costs with the agilent e2920 pci series, case study, p/n 5968-6949e agilent e2920 verification tools, pci series gives altera corporation competitive advantage, case study, p/n 5968-4191e you can find the current literature and software at: www.agilent.com/find/pci_products for more information, please visit us at: www.agilent.com/find/pci_overview by internet, phone, or fax, get assistance with all your test & measurement needs online assistance: www.agilent.com/find/assist phone or fax united states: (tel) 1 800 452 4844 canada: (tel) 1 877 894 4414 (fax) (905) 206 4120 europe: (tel) (31 20) 547 2000 japan: (tel) (81) 426 56 7832 (fax) (81) 426 56 7840 latin america: (tel) (305) 267 4245 (fax) (305) 267 4286 australia: (tel) 1 800 629 485 (fax) (61 3) 9272 0749 new zealand: (tel) 0 800 738 378 (fax) 64 4 495 8950 asia pacific: (tel) (852) 3197 7777 (fax) (852) 2506 9284 product specifications and descriptions in this document subject to change without notice. copyright ? 2002 agilent technologies printed in germany june 12, 2002 5968-8984e www.agilent.com/find/emailupdates get free email updates --------------------------------- keep up to date with agilent's free email updates. as a subscriber, you will receive regular, customized email updates on the topics you select. updates cover support, products and ser- vices, applications, promotions, events, and other areas. it is easy to unsubscribe or change your preferences. subscribe today: http://www.agilent.com/find/emailupdates. agilent is committed to respecting and protecting your privacy. our privacy statement at http://www.agilent.com/go/privacy describes our commitment to you. please direct any ques- tions about agilent's privacy program to privacy_advo- cate@agilent.com. |
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